The invention relates to a semiconductor device having a digital-to-analog converters (DACs) for use in digital TV set, DVDs, and game machines, and more particularly to such semiconductor device having DACs suitable for testing the semiconductor device. The invention also relates to a method of testing a semiconductor device.
In digital TV sets, DVDs, and game machines, data processing of a video signal for example is first performed in digital form and then the digital data is converted to an analog data prior to outputting the data. To perform the conversion, a DAC is used. Of course such DAC is integrated in an integrated circuit, so that a dedicated tester is used to assess its performance.
FIG. 1 is a block diagram representation of a conventional semiconductor 100 having a DAC. As shown in FIG. 1, the semiconductor device 100 is provided with n-bit digital input signal Din and a clock CLK. The input signal Din is latched in a latch circuit 101, decoded in a decoder 102, and then converted into an analog signal by a DAC 103. The converted analog signal is output from the DAC as the analog output signal Dout.
In testing the semiconductor device 100, it is connected to a tester 110. The tester 110 provides to the semiconductor device 100 a digital input signal Din and a clock CLK which are identical to the signals actually supplied to the semiconductor device 100. The output analog signal Dout is assessed by the tester.
When the semiconductor device 100 is designed for a high-frequency (e.g. 135 MHz) video signal, the performance of the DAC in the high-frequency range must be verified. In general, distortions of the output analog signal Dout are measured for a given digital input signal Din to analyze various characteristics of the DAC 103. To do this, the tester 110 provides a digital sinusoidal wave signal and a clock to the semiconductor device 100, and distortions of the analog signal output from the semiconductor device 100 are measured by a spectrum analyzer set up in the tester 110.
Thus, in testing the semiconductor device having a DAC, a tester capable of outputting high frequency signals in different test modes is necessary. That is, the high-frequency tester 110 must be capable of realizing various problematic conditions that it might encounter in the measurements of high frequency signals as output from the semiconductor device, for example variation in capacitance of wires, signal delays in the wires, and timing violation in the semiconductor. Because of this requirement, the tester is considerably expensive as compared with ordinary mass-produced testers (e.g. testers designed to output a signal of 40 MHz). Consequently, a capital investment for the testers greatly affects the manufacturing cost of the semiconductor device having a DAC.
It is therefore an object of the invention to provide a semiconductor device having DACs that can be successfully tested in various high-frequency modes without using a tester capable of outputting high-frequency digital test signals.
It is another object of the invention to provide a method of testing a semiconductor device having such DACs.
In accordance with one aspect of the invention, there is provided a semiconductor device equipped with at least one channel of DAC for converting a digital signal input to the semiconductor device into an analog signal before it is output from the semiconductor device, the semiconductor device comprising:
test pattern generation means for storing and generating test patterns; and
a clock input terminal which can receive a test clock during a test, wherein
the test pattern generation means generates a digital test signal representing a test pattern based on a test clock supplied to the clock input terminal during a test, and provides the digital test signal and the test clock to the DAC channel.
In testing the semiconductor device equipped with such DAC according to the invention, the device only require a fast test clock, which can be easily generated and supplied from an external clock generator. Based on this test clock, a high-frequency digital test signal representing a prescribed test pattern can be generated by the test pattern generation means and provided to the DAC channel, so that the DAC can be tested for the high-frequency signal as in the test using a high-frequency tester.
Therefore, although the semiconductor device requires therein such pattern generation means, it can be provided at low cost since no expensive tester generating a high frequency test signal is required to test the device.
The semiconductor device may further comprise a test mode input terminal for receiving a test mode signal indicative of a test mode supplied to the test pattern generation means so that, based on the test clock received through the test clock terminal during a test, the test pattern generation means generates a digital test signal representing the test pattern designated by the test mode signal.
In this way, many of the characteristics of the DAC can be tested using different test patterns in accord with various test modes.
The semiconductor device may comprise an additional test power supply terminal for supplying a voltage higher than the operating voltage of the DAC to the test pattern generation means. This will improve the performance of the test pattern generation means and allow it to operate at a higher speed. Thus, it is possible to minimize the size of the test pattern generation means while driving it faster, which helps minimization of the chip size of the semiconductor device.
The semiconductor device shown herein has six channels of DACs (referred to as DAC channels) such that the three DACs in the first three DAC channels and the three DACs in the second three DAC channels can be separately tested. The first three channels include a composite signal channel, a brightness channel, and a chromatic signal channel, while the second three channels include a brightness signal channel, a first color difference signal channel, and a second color difference signal channel. Hence, six channels can be tested using three testing elements by switching the first and the second three channels.
The semiconductor device has a multiplicity of DAC channels such that the DACs in the respective channels can be individually tested. This can be done by turning off the DACs (thereby causing the DACs to generate outputs at an intermediate level), except one DAC. This arrangement enables measurement of cross talks between the active (ON) channel and rest of the inactive (OFF) channels.
The test pattern generation means may store sinusoidal wave test patterns to generate a sinusoidal wave test pattern in accord with a designated test mode when said test mode is a sinusoidal wave test mode. These sinusoidal wave test patterns have different combinations of frequencies, amplitudes, and DC biases in combination. In some of the test modes, the sinusoidal wave test pattern has an arbitrary number of the lower bits fixed to zero.
In such test mode, the level and/or the distortion of a high-frequency signal can be tested. Different frequencies, levels (in amplitude/accuracy) and DC biases may be used in combination to carry out varied sinusoidal wave tests. In addition, bit-drop by the DAC may be tested by evaluating the level of the analog signal output therefrom, based on the fact that the level of the output analog signal varies if the input digital signal is missing certain bits.
The test pattern generation means may store square wave test patterns to generate a square wave test pattern in accord with a designated test mode when the test mode is a square wave test mode. These square wave test patterns have different periods, duty cycles, amplitudes, and DC biases in combination. The amplitude of the square wave pattern may have an arbitrary number of lower bits fixed to zero.
In these square wave test modes, it is possible to evaluate glitch energy and the transient response of the DAC at the rise/fall of the signal. Various tests may be also carried out using different square wave test patterns having different periods, duty cycles, levels (amplitudes/precisions), and DC biases. In addition, bit-drop by the DAC may be tested by evaluating the level of the analog signal output therefrom, based on the fact that the level of the output analog signal varies if the input digital signal is missing certain bits.
The DAC may be a current additive type DAC which comprises:
a set of multiple conversion units connected in parallel, each unit having a constant current element controlled by a reference potential and a switching element connected in series with said constant current element and adapted to be turned ON/OFF by a control signal based on the input digital data;
reference potential generation means for generating said reference potential;
a reference potential line for providing said reference potential to each of said constant current elements of said conversion units, wherein
the reference potential generation means has a potential feedback means for setting low its impedance of the reference generation means as viewed from the reference potential line.
In this arrangement of the current additive type DAC, the impedance of the reference potential generation means is set low as viewed from the reference potential line so that the cutoff frequency as determined by the floating static capacitance and the impedance of the reference potential generation means is shifted to a higher frequency, so that the variation of the reference potential on the reference potential line is reduced, resulting in a high fidelity D/A conversion.
In accordance with the invention, there is provided a method of testing a semiconductor device having DACs for converting digital signals into analog signals, utilizing a tester having a slower processing speed than the DACs, wherein the tester has means for generating a test clock; the semiconductor device has test pattern generation means for storing and generating test patterns for testing at least a portion of the performance of the DACs, and a clock input terminal which can receive the test clock to drive the test pattern generation means by the test clock, said method comprising steps of:
supplying a test clock from the tester to the test pattern generation means via said clock input terminal;
causing the test pattern generation means to generate a digital test signal in synchronism with the test clock;
supplying the test clock and the digital test signal to the DACs to convert the digital test signal into an analog signal; and
assessing the analog signal by the tester.
The method of the invention allows tests of the DACs at high frequency without using an expensive tester that generates high-frequency digital test signals.